Close functional coverage — and prove it, not just claim it.
averify is an AI agent that writes, runs, debugs, and repairs cocotb testbenches for your RTL on open-source simulators, iterating until functional coverage closes. Every closed run is independently cross-checked on a second simulator engine and every covered bin is traced back to the exact spec requirement it satisfies — so the coverage number is something you can actually trust, not just a percentage on a dashboard.
Verification is where chip projects lose time and money.
Hand-writing and debugging testbenches to hit coverage closure is the most labor-intensive part of getting a design to tape-out. averify automates that loop — on the open-source toolchain, with a second engine watching its work — so teams without enterprise EDA licenses can move at the pace their schedule actually needs.
Open-source flow
Runs on Icarus and Verilator with cocotb in Python. No Xcelium or VCS license required to start.
Built for RISC-V
Proven on a real RISC-V core, not a toy DUT, and scored on NVIDIA's CVDP dataset — a third-party benchmark, not a number we made up.
Runs on your infrastructure
Deploy on your own machines — your RTL never has to leave your environment. Multi-tenant orgs, roles, and a full audit log come standard for teams.
One agent loop, from spec to coverage closure.
Give averify your RTL and a spec. The agent runs a closed loop until checks pass and functional coverage meets your target.
Plan
Parses the design interface and reads the spec to plan what needs to be exercised.
Write the testbench
Generates a cocotb (Python) testbench with stimulus, checkers, and a functional coverage model.
Simulate
Compiles and runs against the design on Icarus or Verilator, capturing pass/fail and coverage.
Analyze
Reads the results and the coverage report, identifies what failed or what is still uncovered.
Repair & iterate
Fixes the test and adds stimulus to reach uncovered bins — looping until coverage closes or it reports an honest gap.
Cross-check & trace
On close, the winning testbench is re-run on the other open-source engine as a second opinion, and every covered bin is mapped back to the spec requirement it proves.
averify repairs the test — never your design. It will not edit the RTL under verification, and it never games the coverage number. Every run's full distribution is visible, so a result you can't trust is a result that isn't worth having.
A coverage number is only as good as what stands behind it.
Most agentic tools hand you a pass/fail and a percentage and ask you to take their word for it. averify backs every closed run with two independent checks, so "closed" means something.
⇄ Dual-simulator cross-check
Every CLOSED run's winning testbench is automatically re-run on the other open-source engine — Icarus if the primary was Verilator, or vice versa. A second, independent implementation has to agree before you'd ever call it done. Disagreements surface as a signal, never silently.
◈ Coverage-to-spec traceability
Not just "87% covered" — a table mapping every functional coverage bin to the literal spec requirement it satisfies. Auditable, reviewable, and exportable, so a coverage report can survive a design review, not just a CI badge.
✓ Benchmarked, not just claimed
Scored against NVIDIA's CVDP (Comprehensive Verilog Design Problems) dataset — a third-party benchmark averify runs against reproducibly, so results aren't graded on our own curve.
The agent debugs hardware, live.
A three-minute run: from an empty testbench to closed coverage on a real RISC-V core, with the agent finding and fixing issues along the way.
Don't take our word for it. Run it.
averify's results are reproducible end to end on open-source simulators, and its CVDP adapter lets you score it yourself against NVIDIA's public benchmark. Clone the repo, run one command, and watch the agent close coverage on a real RISC-V core on your own machine.
Pricing that scales with usage, not headcount.
Start free, move to Pro when your team needs more room, and talk to us for a negotiated Enterprise rate — seats, orgs, and audit trail included at every tier.
Want to try averify on your RTL?
If you're working on RISC-V, open-hardware, or a cost-sensitive verification flow — or you just want to see a run — reach out. Early design partners get hands-on access.